Optimization of Parallel Random Access Machine (PRAM)

Abstract

Parallelism at the hardware level has become more advanced. Earlier one was able to model the parallel advances as a constant speed-up due the fact that the degree of parallelism was rather small. It was done over the classical RAM model. But the continuous growth of parallelism makes that assumption invalid. During the next decade the number of cores integrated into a single chip is very likely to grow. It is obvious that the sequential RAM will not accurately model the parallelism of the modern architecture. In this research we propose a new model over the classical PRAM model which has been widely used for a long time period for the parallel algorithms analysis. The new model still builds upon the RAM and PRAM. The proposed model supports a high-level abstraction that make it simple to design and analyse parallel algorithms when compared to the classical PRAM